ASIC Physical Design Engr, Sr II
Job Description and Requirements
Synopsys semiconductor IP, is at the heart of innovations that are changing the way we live and work.
The Internet of Things, self-driving vehicles, mobile devices, high definition media, machine learning and computer vision.
These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them.
Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools and IP, for silicon chip design and verification, and application security testing.
Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
The ASIC Digital Implementation team in Porto, Portugal, is looking for a Senior ASIC Physical Design Engineer, who provides technical leadership and develops of high quality, leading edge, semiconductor IP and Test Chips
An important part of the role is to provide proper feedback to architecture and digital/analog design, teams about floorplan, power plan and timing constraints and closure, as well as to ensure clean physical verification, track and ensure on-time incoming and outgoing deliveries.
This role also requires collaboration with several teams located in multiple Synopsys offices, provide clear and concise management reporting and mentor junior team members.
· Independently work in all place and route flow stages: Synthesis, Floorplan, Power Plan, Placement, CTS, Routing, STA and Physical Verification
· Represent the implementation team in project meetings
· Track and ensure on-time incoming and outgoing deliveries, and report on project progress
· Coach and mentor junior team members
· Provide technical feedback to design teams, management or customer support team.
· A relevant degree in electrical engineering or computer science
· Significant experience in ASIC physical implementation and place and route flows
· Knowledge of industry standard data file formats: Verilog, GDSII, LEF, DEF, SDF, LIB
· Scripting and programing skills: TCL, Unix Shell, Python
· Verbal and written fluency in English
· Strong cross team communication skills, team leading experience and tuition of junior engineers
· Practical experience with any P&R tool set
· Proficiency in C++
· Practical experience with Synopsys PnR tool set: Design Compiler, IC Compiler (2), Prime Time, IC Validator
· Interesting work in international team
· Salary is based on experience, professional background, interview/test results
· Flexible work schedule
· Social package (bonus program, major medical insurance for employee and optionally for family members, corporate events, etc.)
PORTUGAL - Porto, PORTUGAL - Portugal